In a technical area of a processor, it is difficult to improve performance by a single core due to problems with respect to a limitation of a clock operation frequency, heat generation and power consumption. Therefore, in recent years, an architecture, in which total performance is exhibited by mounting a plurality of cores in a chip, becomes mainstream.
In a case of a sharing-memory-type processor in which a plurality of cores share a memory, it is necessary to construct a network that connects each core to the memory. However, with an increase in the number of cores, it is difficult to directly connect all cores to the memory due to problems regarding a limitation of the number of transistors which are capable of being mounted in an LSI (Large Scale Integration) chip, and a wiring property. Therefore, it is realistic to indirectly connect the cores to the memory by utilizing topologies which are a mesh, a ring and the like. In this case, distances between the cores and the memory may not be equal, and arbitration (competition arbitration) may occur for competition between a memory request by an own core and a memory request by another core in each point in the network. When load of the network is increased by such a reason, it is determined that a state generally called congestion occurs. When the congestion state has occurred, memory latency increases and replies for memory load commands are out of order. Therefore, system performance degrades considerably. Particularly, in a HPC (High Performance computing) field, since the improvement of memory access performance is one of the most important performance parameters, a technology for avoiding this problem becomes very important.
As a technology related to such a technology, PTL1 (Japanese Unexamined Patent Application Publication No. 2007-094657) discloses a technology related to a memory access control method in which each processor autonomously predicts a memory load in a multiprocessor system. This technology prevents processing from being stopped by a busy signal.
PTL 2 (Japanese Unexamined Patent Application Publication No. 2006-172243) discloses a technology related to a fault-tolerant computer device in which a plurality of computer systems simultaneously perform processing in synchronization with a clock.
PTL 3 (Japanese Unexamined Patent Application Publication No. 2004-110484) discloses a technology related to a memory access device capable of efficiently performing exclusive control.